%$Header: /home/dashley/cvsrep/e3ft_gpl01/e3ft_gpl01/dtaipubs/esrgubka/c_cis0/c_cis0.tex,v 1.3 2002/09/12 23:30:20 dtashley Exp $
\chapter[Solutions: \ccilzeroxrefcomma{}Chapter \ref{ccil0}]
{Solutions: \ccilzeroxrefcomma{}Chapter \ref{ccil0}, \ccilzerolongtitle{}}
\label{ccis0}
\vworkexercisechapterheader{}
\begin{vworkexercisesolution}{\ref{exe:ccil0:sexe0:01}}
We can show this result in two ways. The first way, based on bit patterns, is to note
that adding an $m$-bit number, $u$, to its one's complement will result in a bit pattern
containing all 1's, i.e. $\forall i$, $u_{[i]} = 1$. Adding 1 to this bit pattern will
always produce $\forall i$, $u_{[i]} = 0$ with a carry out. Since the order of addition
does not matter, this establishes that adding $u$ to $\sim{}u+1$ will produce 0, thus showing
that $u$ and $\sim{}u+1$ are additive inverses. This method, although valid, does not
establish that $u$ and $\sim{}u+1$ actually represent additive inverses. For example, if
$u=-2^{m-1}$, $u=\sim{}u+1$, and clearly a non-zero number cannot be an additive inverse of
itself. Thus, it would be more comforting to show this result in a way that demonstrates the
actual values of the integers represented.
We present a second method now. Assume that $u \neq -2^{m-1}$, since
$-2^{m-1}$ cannot have an additive inverse in an $m$-bit signed integer.
If $u=0$, $\sim{}u+1=0$, so the relationship is clearly met. If $u<0$, then
$u_{[m-1]}=1$, and by
(\ccilzeroxrefhyphen\ref{eq:ccil0:sroi0:sros0:00}),
\end{vworkexercisesolution}
\vworkexercisechapterfooter
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\begin{verbatim}
$RCSfile: c_cis0.tex,v $
$Source: /home/dashley/cvsrep/e3ft_gpl01/e3ft_gpl01/dtaipubs/esrgubka/c_cis0/c_cis0.tex,v $
$Revision: 1.3 $
$Author: dtashley $
$Date: 2002/09/12 23:30:20 $
\end{verbatim}
\end{tiny}
\noindent\rule[0.25in]{\textwidth}{1pt}
\end{figure}
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% Safety checkin as changing machines.
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% Revision 1.2 2002/08/26 17:57:03 dtashley
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% Revision 1.1 2002/08/26 17:35:06 dtashley
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%End of file C_CIS0.TEX